Applications are invited for the Compiler Software Engineer Intern at D-Matrix, Bangalore. Check the eligibility and other details below!
About D-Matrix
D-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI computing has been to break through the memory wall to minimise data movements. D-Matrix achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chipsets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. They are poised to meet these Large Language Models’ energy and performance demands. The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.
Role and Responsibilities
The Compiler Team at d-Matrix is responsible for developing the software that performs the logical-to-physical mapping of a graph expressed in an IR dialect (like Tensor Operator Set Architecture (TOSA), MHLO or Linalg) to the physical architecture of the distributed parallel memory accelerator used to execute it. It performs multiple passes over the IR to apply operations like tiling, compute resource allocation, memory buffer allocation, scheduling and code generation. You will be joining a team of exceptional people enthusiastic about developing state-of-the-art ML compiler technology.
In this role, you will design, implement and evaluate a method for managing floating-point data types in the compiler. You will work under the guidance of two members of the compiler backend team. One is an experienced compiler developer based in the West Coast of the US.
You will engage and collaborate with engineering team in the US to understand the mechanisms made available by the hardware design to perform efficient floating point operations using reduced precision floating point data types.
Successful completion of the project will be demonstrated by a simple model output by the compiler incorporating the your code that executes correctly on the hardware instruction set architecture (ISA) simulator. This model incorporates various number format representations for reduced precision floating point.
Qualifications
- Bachelor’s degree in computer science or equivalent 3 years towards an Engineering degree with emphasis on computing and mathematics coursework.
- Proficiency with C++ object-oriented programming is essential.
- Understanding of fixed point and floating-point number representations, floating point arithmetic, reduced precision floating point representations and sparse matrix storage representations and the methods used to convert between them.
- Some experience in applied computer programming (e.g. prior internship).
- Understanding of basic compiler concepts and methods used in creating compilers (ideally via a compiler course).
- Data structures and algorithms for manipulating directed acyclic graphs.
Desired Skill Sets
- Familiarity of sparse matrix storage representations.
- Hands on experience with CNN, RNN, Transformer neural network architectures
- Experience with programming GPUs and specialized HW accelerator systems for deep neural networks.
- Passionate about learning new compiler development methodologies like MLIR.
- Enthusiastic about learning new concepts from compiler experts in the US and a willingness to defeat the time zone barriers to facilitate collaboration.
How to Apply?
Interested candidates can directly apply through this link.
Location
Bangalore, Karnataka.
Duration
This internship position is for 3 months.
