Cisco is inviting applications for RTL Design Engineer at Cisco, Bengaluru. Check below for more details!

About Cisco

Cisco Systems, Inc. is an American multinational technology conglomerate headquartered in San Jose, California, in the center of Silicon Valley. Cisco develops, manufactures, and sells networking hardware, software, telecommunications equipment, and other high-technology services and products.

Job Description

  • We are looking for an expert and talented ASIC Engineer.
  • You will have an ASIC design background with hands-on experience in design, verification, physical design, and system testing, with in-depth knowledge of the ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a consistent track record of success in high-performance/high-volume products.

Department

Cisco’s groundbreaking Service Provider and Enterprise solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc).

Minimum Qualifications

  • Understanding of networking and networking processors.
  • End-to-end design experience from Verilog to gates, block planning, and area/timing closure is helpful.
  • RTL development and verification (VCS, System Verilog, UVM/OVM, Formal verification).
  • Experienced in system debugging and SW/HW bring-up, system validation of silicon towards FCS.
  • Gate-level understanding of RTL and Synthesis.
  • Programming/scripting skills (C, C++, Perl).
  • Hardware Emulation Platforms and tools (such as EVE, and Veloce).
  • 2+ years of meaningful experience.
  • Good written/verbal communication skills and leadership skills.

Desired Skills

  • Worked in architecture and definition of high-scale, high-performance ASICs.
  • Validated experience in implementation: specification, design, verification, formal verification, and system testing.
  • Validated experience in physical design aspects: timing analysis and closure, power/area optimizations, and macro size/placement analysis.
  • Validated experience in high bandwidth memory subsystems and timing closure.
  • Validated experience in flow automation (scripting, Makefile, etc), and established guidelines for the team.
  • Good social skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
  • 4+ years of hands-on experience in large-scale, high-performance ASICs.
  • BE/MS in ECE/CS.

Responsibilities

  • Architectural work: an in-depth understanding of the architecture, and identification of problems and solutions.
  • All aspects of implementation: specification, design, verification, timing-closure, power optimization, and flow automation.
  • Physical design work: timing path analysis, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.
  • Document and improve standard methodologies to make a product successful.
  • Lead other specialists in project achievements: schedule, power, area.

How to Apply?

Interested applicants can apply for the post through this link.

Location

Bangalore, India.

Click here to view the official notification for RTL Design Engineer at Cisco, Bengaluru.