Students and freshers can apply for the Formal Verification Internship at Synopsys, Bangalore. Check the eligibility and other details below!
About Synopsys
Synopsys technology is at the heart of innovations changing how we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
Job Description
As a Formal Verification Engineer at Synopsys, the individual will be responsible for formally verifying complex design IPs. The Synopsys IP Group follows a robust formal verification methodology that allows hardware verification engineers to effectively apply formal verification (FV) tools and techniques to intricate and/or critical RTL logic. The role will involve close collaboration with designers, architects, verification engineers, and the Synopsys Tool Development Group to drive verification projects forward.
Responsibilities
- Help decide on the best applications of formal verification techniques to various parts of the design.
- Review functional and micro-architectural specifications, define the scope for formal verification, and create high-quality formal verification testplans to sign-off on the corresponding design implementation.
- Build formal verification testbenches, code assertions and constraints, and apply abstraction techniques to converge the targeted properties or to achieve reasonable proof-depth.
- Apply formal coverage techniques for analysing over-constraints and for measuring functional coverage.
Required Skill Sets
- Pursuing or completed BTech/ MTech degree
- Good understanding of hardware micro-architecture and design
- Proficiency in HDLs like Verilog, SystemVerilog
- Familiarity with SystemVerilog Assertions (SVA) and basic concepts of formal property verification
- Good debugging and problem-solving skills
- Scripting knowledge (Python/Perl/shell)
- Good interpersonal and communication skills and dream to work as a great team
- Academic projects related to formal verification or digital design verification
- Exposure to formal verification tools like VCFormal, Jasper, Yosys etc
- Knowledge of protocols like AXI, CHI, PCIe, DDR, etc
How to Apply?
Interested candidates can directly apply through this link.
Stipend
- ₹5 Lakhs – ₹6.3 Lakhs/Year
- Note: Stipend information is taken from here!
Location
Bengaluru, Karnataka, India
