Online applications are invited for the Hardware Engineer for Test Verification Simulation and Productization at Google, Bangalore. Check the details below!
About Google
Google is an American MTC focused on search engine technology, online ad, Cloud Computing, Computer Software, E-Commerce, AI, and customer electronics. Google has many unique traits to help you find exactly what you’re looking for.
Job Description
- Google’s computational challenges are so big, complex and unique that we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves.
- Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure.
- You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high-volume manufacturing.
- Your work has the potential to shape the machinery that goes into our cutting-edge data centres affecting millions of Google users.
- With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data centre facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Responsibilities
- Partner with the ATE team on Silicon Debug and ensure the stability of the pattern across voltage/temperature/process corners.
- Explore new flows, simulation tools, and ideas for continuous improvement.
- Work with the SoC Development team to Verify/simulate/debug FUNC/HSIO blocks RTL/Gate level, ATE/Bench pattern generation with coverage and Silicon Debug.
- Understand the SoC level DV/UVM environment, JTAG/APB/AHB/AXI based protocols, and the requirements for verifying SubSystems on SOC level.
Minimum Qualifications
- Bachelor’s degree in Engineering or equivalent practical experience.
- 2 years of experience working in SoC Chip level/Cluster/Sub-System Verification.
- Experience in ARM Cores, AMS and HSIO PHY (USB2, USB3, PCIE PHY, MIPI PHY, UFS PHY) design verification, and Test bench creation.
Preferred Qualifications
- Experience with DV Env and Test case development for RTL verification, Gate Level (GLS) Verification, Timing (SDF) GLS and Power Aware (PAGLS) verification with Synopsys/Mentor or Cadence, or equivalent tools.
- Experience in ATE pattern generation/conversion, Virtual Tester simulation, and Bench CSV generation.
- Familiarity with JTAG/APB/AHB/AXI-based protocols, and experience with design and debugging of functional/AMS/HSIO patterns on ATE/Bench.
- Knowledge of HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog).
- Familiarity with different test pattern formats such as STIL, WGL, SVF, VCD, eVCD, and ATE fail catalogues.
How to Apply?
Interested candidates can directly apply through this link.
Salary
Estimated Take-Home Salary: ₹ 1,80,033 – ₹ 1,87,037/month
Note: Salary information is taken from here!
Location
Bangalore, Karnataka
