Online applications are invited for the VLSI Intern at Seagate, Pune. Check the eligibility and other details below!
About Seagate
Seagate empowers humanity to thrive in the data age and helps people and businesses navigate the ever-expanding data landscape. Seagate crafts precision-engineered, cutting-edge solutions that help the world store and manage exponential data growth. Powered by a talented, passionate, and diverse workforce of 40,000 employees globally, Seagate remains committed to its core values: integrity, innovation, and inclusion.
Job Description
The group is part of Seagate’s VLSI Organization spread globally across multiple sites. Seagate designs world class controller SoCs for their HDDs. The group in Pune participates in design, verification, physical design and post-silicon validation activities of these complex SoCs. This group has some of the best talent from the industry and has taped out many controller chips.
Roles & Responsibilities
- Be able to work on block level Physical Design implementation using EDA tools for floorplanning, placement and timing analysis
- Understand Semicustom IC design flow using IP libraries, concepts of Verilog netlist, meaning of timing constraints and QOR checks
- Work on Physical design tasks including floor-planning, placement, clock tree synthesis, routing, timing analysis and equivalence checking for designs
- Work on Timing analysis for sign-off corners and modes, report generation, analysis of the reports and suggesting timing/DRC fixes to fix the violations
- Complete internship project as per plan
Required Skill Sets
- Knowledge of ASIC design flow and tools
- Good understanding of Circuit design and Logic design
- Good understanding of analog circuit design and concepts
- Good understanding of timing concepts like setup time, hold time requirements, calculations of maximum
- Understanding Frequency of circuit operations, effect of transition and load on circuit performance and power
- Basic understanding of CMOS fabrication process
- Basic understanding of layout design for CMOS and BJT
- Basic understanding of power dissipation in different types of circuits
- Self-motivated & a strong team player
- Strong analytical skills
- Ability to quickly learn new tools and technologies
- Your experience includes:
- ASIC design flow, basic EDA tools for Physical design implementation
- Place and Route, Timing Analysis, Equivalence check
- Perl, Tcl, Shell or other scripting languages
Location
This position is based in Pune, India.
How to Apply?
Interested candidates can directly apply through this link.
Stipend
- ₹ 5,64,854 per annum.
- Note: Stipend information is taken from here!
